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General Information
    • ISSN: 1793-8244 (Print)
    • Abbreviated Title:  J. Adv. Comput. Netw.
    • Frequency: Semiyearly
    • DOI: 10.18178/JACN
    • Editor-in-Chief: Professor Haklin Kimm
    • Executive Editor: Ms. Cherry Chan
    • Abstracting/ Indexing: EBSCO, ProQuest, and Google Scholar.
    • E-mail: jacn@ejournal.net
    • APC: 500USD
Professor Haklin Kimm
East Stroudsburg University, USA
I'm happy to take on the position of editor in chief of JACN. We encourage authors to submit papers on all aspects of computer networks.

JACN 2020 Vol.8(1): 14-20 ISSN: 1793-8244
DOI: 10.18178/JACN.2020.8.1.274

Design and VLSI Implementation of Low Latency IEEE 802.11i Cryptography Processing Unit

Jun-Dian Li and Chih-Peng Fan

Abstract—IEEE 802.11i is the important security standard for wireless local area network, and it includes three security functions, which are WEP, TKIP, and CCMP, to provide the data confidentiality. In this paper, the effective cipher architecture of IEEE 802.11i is developed to achieve the low-latency application. For the cryptography processing functions, the cipher core of WEP and TKIP is the RC4 algorithm, and that of the CCMP is the AES algorithm. For a ciphered packet by WEP and TKIP, the RC4 operations need a constant latency, which generates the excessively low throughput when the packet length is too short. For the low-latency design, the 16-bit packed memory algorithm is applied to reduce the constant latency in the RC4 computations. To reduce the hardware cost of CCMP for the byte-wise data transmission in IEEE 802.11, the 32-bit AES architecture is used in place of the conventional 128-bit AES design. For VLSI implementation, the proposed low-latency IEEE 802.11i cryptography processing architecture is synthesized by Synopsys Design Compiler with TSMC 0.18um technology. Excluding the cost of memory module, the proposed design for cipher computations requires about 44,300 gate counts, and the maximum operational frequency is 51MHz. Besides, the power consumption of the processing unit at 50MHz is 12.61mW.

Index Terms—IEEE 802.11i, cryptography, low latency, VLSI implementation.

Jun-Dian Li and Chih-Peng Fan are with the Department of Electrical Engineering, National Chung Hsing University, 145 Xingda Rd., South Dist., Taichung City 402, Taiwan (e-mail: jundian@gmail.com, cpfan@dragon.nchu.edu.tw).


Cite:Jun-Dian Li and Chih-Peng Fan, "Design and VLSI Implementation of Low Latency IEEE 802.11i Cryptography Processing Unit," Journal of Advances in Computer Networks vol. 8, no. 1, pp. 14-20, 2020.

Copyright © 2020 by the authors. This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).
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