—Modern On-chip Multi-core design will continue
Moore’s law and facilitate platforms for wired and wireless
communications. It has been predicted that the future
computing platform will have a tightly integrated complex
system that can process “big data” with swift speed and high
quality. However, it is not clear how the current multi-core
systems would react to large volume of data and how the data
volume would impact the interconnect network design and
architecture of the future computing platform. The goal of this
paper is to raise these questions and provide some answers. In
particular, this paper provides a series of cost models and a
new optimization scheme “Interconnect Communication Cost
Minimization” (ICCM) to manage tasks and their data. Task
flows and their partitions are considered with data amount
created and consumed. The consequent partitions are mapping
virtually to the multi-core system through a data and task
scheduling optimizer. Through experimental results, we
demonstrated that an average of 50% reduction in the
communication cost, an average of 23.1% of throughput
improvement and 35% of dynamic power reduction.
—Multi-core, data-centric design, interconnect
communication cost minimization, accuracy adaptive adder.
He Zhou is with the University of Arizona, Tucson, AZ 85721 USA (email:
Mariya Bhopalwala is with the University of Arizona, Tucson, AZ
85721 USA (e-mail: firstname.lastname@example.org).
Janet Roveda is with the University of Arizona, Tucson, AZ 85721
USA (e-mail: email@example.com).
Cite:He Zhou, Mariya Bhopalwala, and Janet Roveda, "On-Chip Interconnect Network Communication Management for Multi-Core Design," Journal of Advances in Computer Networks vol. 1, no. 3, pp. 194-200, 2013.