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General Information
    • ISSN: 1793-8244
    • Frequency: Semiyearly
    • DOI: 10.18178/JACN
    • Editor-in-Chief: Dr. Ka Wai Gary Wong
    • Executive Editor: Ms. Nina Lee
    • Abstracting/ Indexing: EI (INSPEC, IET), Engineering & Technology Digital Library, DOAJ, Electronic Journals Library, Ulrich's Periodicals Directory, International Computer Science Digital Library (ICSDL), ProQuest, and Google Scholar.
    • E-mail: jacn@ejournal.net
Editor-in-chief
Dr. Ka Wai Gary Wong
Division of Information and Technology Studies, Faculty of Education, The University of Hong Kong.
It's a honor to serve as the editor-in-chief of JACN. I'll work together with the editors and reviewers to help the journal progress
JACN 2013 Vol.1(3): 194-200 ISSN: 1793-8244
DOI: 10.7763/JACN.2013.V1.39

On-Chip Interconnect Network Communication Management for Multi-Core Design

He Zhou, Mariya Bhopalwala, and Janet Roveda
Abstract—Modern On-chip Multi-core design will continue Moore’s law and facilitate platforms for wired and wireless communications. It has been predicted that the future computing platform will have a tightly integrated complex system that can process “big data” with swift speed and high quality. However, it is not clear how the current multi-core systems would react to large volume of data and how the data volume would impact the interconnect network design and architecture of the future computing platform. The goal of this paper is to raise these questions and provide some answers. In particular, this paper provides a series of cost models and a new optimization scheme “Interconnect Communication Cost Minimization” (ICCM) to manage tasks and their data. Task flows and their partitions are considered with data amount created and consumed. The consequent partitions are mapping virtually to the multi-core system through a data and task scheduling optimizer. Through experimental results, we demonstrated that an average of 50% reduction in the communication cost, an average of 23.1% of throughput improvement and 35% of dynamic power reduction.

Index Terms—Multi-core, data-centric design, interconnect communication cost minimization, accuracy adaptive adder.

He Zhou is with the University of Arizona, Tucson, AZ 85721 USA (email: hezhou@email.arizona.edu).
Mariya Bhopalwala is with the University of Arizona, Tucson, AZ 85721 USA (e-mail: mariyab@email.arizona.edu).
Janet Roveda is with the University of Arizona, Tucson, AZ 85721 USA (e-mail: wml@ece.arizona.edu).

[PDF]

Cite:He Zhou, Mariya Bhopalwala, and Janet Roveda, "On-Chip Interconnect Network Communication Management for Multi-Core Design," Journal of Advances in Computer Networks vol. 1, no. 3, pp. 194-200, 2013.

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